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1 i n d e v e l o p m e n t memory array column i/o input drivers input drivers row decoder output enable e2 w g e1 chip enable output drivers data write circuit data read circuit column decoder write enable input drivers input drivers top/bottom decoder block decoder input drivers a(18:0) input driver dq(7:0) figure 1. ut8r512k8 sram block diagram features q 10ns maximum access time q asynchronous operation for compatibility with industry- standard 512k x 8 srams q cmos compatible inputs and output levels, three-state bidirectional data bus - i/o voltage 2.5 to 3.3 volts, 1.8 volt core q radiation performance - intrinsic total-dose: 100k rad(si) - sel immune >128 mev-cm 2 /mg - onset let > 24 mev-cm 2 /mg - memory cell saturated cross section, 1.0 x 10 -8 cm 2 /bit - 1.0e x 10 -10 errors/bit-day, adams to 90% geosynchronous heavy ion - neutron fluence: 3.0e14n/cm 2 - dose rate - upset 1.0e9 rad(si)/sec - latchup >1.0e11 rad(si)/sec q packaging options: - 36-lead ceramic flatpack q standard microcircuit drawing pending - qml compliant part introduction the ut8r512k8 is a high-performance cmos static ram organized as 524,288 words by 8 bits. easy memory expansion is provided by active low and high chip enables ( e1 , e2), an active low output enable ( g ), and three-state drivers. this device has a power-down feature that reduces power consumption by more than 90% when deselected . writing to the device is accomplished by taking chip enable one ( e1 ) input low, chip enable two (e2) high and write enable ( w ) input low. data on the eight i/o pins (dq0 through dq7) is then written into the location specified on the address pins (a0 through a18). reading from the device is accomplished by taking chip enable one ( e1 ) and output enable ( g ) low while forcing write enable ( w ) and chip enable two (e2) high. under these conditions, the contents of the memory location specified by the address pins will appear on the i/o pins. the eight input/output pins (dq0 through dq7) are placed in a high impedance state when the device is deselected ( e1 high or e2 low), the outputs are disabled ( g high), or during a write operation ( e1 low, e2 high and w low). standard products ut8r512k8 512k x 8 sram advanced data sheet august 29, 2002
2 i n d e v e l o p m e n t pin names device operation the ut8r512k8 has four control inputs called enable 1 ( e1 ), enable 2 (e2), write enable ( w ), and output enable ( g ); 19 address inputs, a(18:0); and eight bidirectional data lines, dq(7:0). e1 and e2 device enables control device selection, active, and standby modes. asserting e1 and e2 enables the device, causes i dd to rise to its active value, and decodes the 19 address inputs to select one of 524,288 words in the memory. w controls read and write operations. during a read cycle, g must be asserted to enable the outputs. table 1. device operation truth table notes: 1. ?x? is defined as a ?don?t care? condition. 2. device active; outputs disabled. read cycle a combination of w and e2 greater than v ih (min) and e1 less than v il (max) defines a read cycle. read access time is measured from the latter of device enable, output enable, or valid address to valid data output. sram read cycle 1, the address access in figure 3a, is initiated by a change in address inputs while the chip is enabled with g asserted and w deasserted. valid data appears on data outputs dq(7:0) after the specified t avqv is satisfied. outputs remain active throughout the entire cycle. as long as device enable and output enable are active, the address inputs may change at a rate equal to the minimum read cycle time (t avav ). sram read cycle 2, the chip enable-controlled access in figure 3b, is initiated by e1 and e2 going active while g remains asserted, w remains deasserted, and the addresses remain stable for the entire cycle. after the specified t etqv is satisfied, the eight-bit word addressed by a(18:0) is accessed and appears at the data outputs dq(7:0). sram read cycle 3, the output enable-controlled access in figure 3c, is initiated by g going active while e1 and e2 are asserted, w is deasserted, and the addresses are stable. read access time is t glqv unless t avqv or t etqv have not been satisfied. a(18:0) address w writeenable dq(7:0) data input/output g output enable e1 enable v dd1 power (1.8v) e2 enable v dd2 power (2.5v) v ss ground 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 13 24 14 23 15 22 16 21 17 20 18 19 figure 2. 10ns sram pinout (36) e2 a18 a17 a16 a15 g dq7 dq6 v ss v dd1 dq5 dq4 a14 a13 a12 a11 a10 v dd2 a0 a1 a2 a3 a4 e1 dq0 dq1 v dd1 v ss dq2 dq3 w a5 a6 a7 a8 a9 g w e2 e1 i/o mode mode x x x 1 3-state standby x x 0 x 3-state standby x 0 1 0 data in write 1 1 1 0 3-state read 2 0 1 1 0 data out read
3 i n d e v e l o p m e n t write cycle a combination of w and e1 less than v il (max) and e2 greater than v ih (min) defines a write cycle. the state of g is a ?don?t care? for a write cycle. the outputs are placed in the high-impedance state when either g is greater than v ih (min), or when w is less than v il (max). write cycle 1, the write enable-controlled access in figure 4a, is defined by a write terminated by w going high, with e1 and e2 still active. the write pulse width is defined by t wlwh when the write is initiated by w , and by t etwh when the write is initiated by e1 or e2. unless the outputs have been previously placed in the high-impedance state by g , the user must wait t wlqz before applying data to the nine bidirectional pins dq(7:0) to avoid bus contention. write cycle 2, the chip enable-controlled access in figure 4b, is defined by a write terminated by the latter of e1 or e2 going inactive. the write pulse width is defined by t wlef when the write is initiated by w , and by t etef when the write is initiated by either e1 or e2 going active. for the w initiated write, unless the outputs have been previously placed in the high-impedance state by g , the user must wait t wlqz before applying data to the eight bidirectional pins dq(7:0) to avoid bus contention. radiation hardness the ut8r512k8 sram incorporates special design and layout features which allows operation in a limited radiation environment. table 2. radiation hardness design specifications 1 notes: 1. the sram is immune to latchup. 2. 10% worst case particle environment, geosynchronous orbit, 0.025 mils of aluminum. supply sequencing no supply voltage sequencing is required between v dd1 and v dd2 . total dose 100k rad(si) heavy ion error rate 2 1.0e-10 errors/bit-day
4 i n d e v e l o p m e n t absolute maximum ratings 1 (referenced to v ss ) notes: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. e xposure to absolute maximum rating conditions for extended periods may affect device reliability and performance. 2. maximum junction temperature may be increased to +175 c during burn-in and steady-static life. 3. test per mil-std-883, method 1012. recommended operating conditions symbol parameter limits v dd1 dc supply voltage -0.3 to 2.0v v dd2 dc supply voltage -0.3 to 3.8v v i/o voltage on any pin -0.3 to 3.8v t stg storage temperature -65 to +150 c p d maximum power dissipation 1.2w t j maximum junction temperature 2 +150 c q jc thermal resistance, junction-to-case 3 5 c/w i i dc input current 5 ma symbol parameter limits v dd1 positive supply voltage 1.7 to 1.9v v dd2 positive supply voltage 2.25 to 3.6v t c case temperature range -55 to +125 c v in dc input voltage 0v to v dd2
i n d e v e l o p m e n t 5 dc electrical characteristics (pre and post-radiation)* (-55 c to +125 c) notes: * post-radiation performance guaranteed at 25 c per mil-std-883 method 1019 at 1.0e5 rad(si). 1. measured only for initial qualification and after process or design changes that could affect input/output capacitance. 2. supplied as a design limit but not guaranteed or tested. 3. not more than one output may be shorted at a time for maximum duration of one second. 4. v ih = v dd2 (max), v il = 0v. symbol parameter condition min max unit v ih high-level input voltage .7* v dd2 v v il low-level input voltage .3* v dd2 v v ol1 low-level output voltage i ol = 8ma,v dd2 =v dd2 (min) .2* v dd2 v v oh1 high-level output voltage i oh = -4ma,v dd2 =v dd2 (min) .8* v dd2 v c in 1 input capacitance | = 1mhz @ 0v 7 pf c io 1 bidirectional i/o capacitance | = 1mhz @ 0v 7 pf i in input leakage current v in = v dd2 and v ss -2 2 m a i oz three-state output leakage current v o = v dd2 and v ss, v dd2 = v dd2 (max) g = v dd2 (max) -2 2 m a i os 2, 3 short-circuit output current v dd2 = v dd2 (max), v o = v dd2 v dd2 = v dd2 (max), v o = v ss -80 +80 ma i dd1 (op 1 ) supply current operating @ 1mhz inputs : v il = v ss + 0.2v v ih = v dd2 + 0.2v, i out = 0 v dd1 = v dd1 (max), v dd2 = v dd2 (max) 1 ma i dd1 (op 2 ) supply current operating @100mhz inputs : v il = v ss + 0.2v, v ih = v dd2 + 0.2v, i out = 0 v dd1 = v dd1 (max), v dd2 = v dd2 (max) 30 ma i dd2 (op 1 ) supply current operating @ 1mhz inputs : v il = v ss + 0.2v v ih = v dd2 + 0.2v, i out = 0 v dd1 = v dd1 (max), v dd2 = v dd2 (max) 5 ma i dd2 (op 2 ) supply current operating @100mhz inputs : v il = v ss + 0.2v, v ih = v dd2 + 0.2v, i out = 0 v dd1 = v dd1 (max), v dd2 = v dd2 (max) 115 ma i dd (sb) 4 total supply current standby a(18:0) static (0hz) cmos inputs , i out = 0 e1 = v dd2 - 0.5, e2 = gnd v dd1 = v dd1 (max), v dd2 = v dd2 (max) 50 ma i dd (sb) 4 total supply current standby a(18:0) @ 10mhz cmos inputs , i out = 0 e1 = v dd2 - 0.5, e2 = gnd, v dd1 = v dd1 (max), v dd2 = v dd2 (max) 55 ma
i n d e v e l o p m e n t 6 ac characteristics read cycle (pre and post-radiation)* (-55 c to +125 c, v dd1 = v dd1 (min), v dd2 = v dd2 (min)) notes: * post-radiation performance guaranteed at 25 c per mil-std-883 method 1019. 1. functional test. 2. three-state is defined as a 500mv change from steady-state output voltage. 3. the et (enable true) notation refers to the latter falling edge of e1 or rising edge of e2. seu immunity does not affect the read parameters. 4. the ef (enable false) notation refers to the latter rising edge of e1 or falling edge of e2. seu immunity does not affect the read parameters. symbol parameter 8r512-10 min max 8r512-15 min max unit t avav 1 read cycle time 10 15 ns t avqv read access time 10 15 ns t axqx 2 output hold time 3 5 ns t glqx 2 g -controlled output enable time 0 0 ns t glqv g -controlled output enable time 5 7 ns t ghqz 2 g -controlled output three-state time 0 5 0 7 ns t etqx 2,3 e-controlled output enable time 3 5 ns t etqv 3 e-controlled access time 10 15 ns t efqz 4 e-controlled output three-state time 2 0 5 0 7 ns
7 i n d e v e l o p m e n t assumptions: 1. e1 and g < v il (max) and w > v ih (min) a(18:0) dq(7:0) figure 3a. sram read cycle 1: address access t avav t avqv t axqx previous valid data valid data assumptions: 1. g < v il (max) and w > v ih (min) a(18:0) figure 3b. sram read cycle 2: chip enable access e1 low or e2 high data valid t efqz t etqv t etqx dq(7:0) figure 3c. sram read cycle 3: output enable access a(18:0) dq(7:0) g t ghqz assumptions: 1. e1 < v il (max) , e2 > and w > v ih (min) t glqv t glqx t avqv data valid
i n d e v e l o p m e n t 8 ac characteristics write cycle (pre and post-radiation)* (-55 c to +125 c, v dd1 = v dd1 (min), v dd2 = v dd2 (min)) notes : * post-radiation performance guaranteed at 25 c per mil-std-883 method 1019. 1. functional test performed with outputs disabled ( g high). 2. three-state is defined as 500mv change from steady-state output voltage. symbol parameter 8r512-10 min max 8r512-15 min max unit t avav 1 write cycle time 10 15 ns t etwh device enable to end of write 7 10 ns t avet address setup time for write ( e1 /e2- controlled) 0 0 ns t avwl address setup time for write ( w - controlled) 0 0 ns t wlwh write pulse width 7 10 ns t whax address hold time for write ( w - controlled) 0 0 ns t efax address hold time for device enable ( e1 /e2- controlled) 0 0 ns t wlqz 2 w - controlled three-state time 0 5 0 7 ns t whqx 2 w - controlled output enable time 3 4 ns t etef device enable pulse width ( e1/ e2 - controlled) 7 10 ns t dvwh data setup time 5 7 ns t whdx data hold time 0 0 ns t wlef device enable controlled write pulse width 7 10 ns t dvef data setup time 5 7 ns t efdx data hold time 0 0 ns t avwh address valid to end of write 7 10 ns t whwl 1 write disable time 3 4 ns
9 i n d e v e l o p m e n t assumptions: 1. g < v il (max). if g > v ih (min) then q(8:0) will be in three-state for the entire cycle. 2. g high for t avav cycle. w t avwl figure 4a. sram write cycle 1: w - controlled access a(18:0) q(7:0) e1 t avav 2 d(7:0) applied data t dvwh t whdx t etwh t wlwh t whax t whqx t wlqz t avwh t whwl e2
i n d e v e l o p m e n t 10 t efdx assumptions & notes: 1. g < v il (max). if g > v ih (min) then q(7:0) will be in three-state for the entire cycle. 2. either e1 scenario above can occur. 3 . g high for t avav cycle. a(18:0) figure 4b. sram write cycle 2: enable - controlled access w e1 d(7:0) applied data e1 q(7:0) t wlqz t etef t wlef t dvef t avav 3 t avet t avet t etef t efax t efax or e2 e2
11 i n d e v e l o p m e n t data retention characteristics (pre-radiation) 3 (t c = 25 c, v dd2 = v dd2 (min), 1 sec dr pulse) symbol parameter minimum maximum unit v dr v dd1 for data retention 1.0 -- v i ddr 1 data retention current -- 10 m a t efr 1,2 chip deselect to data retention time 0 ns t r 1,2 operation recovery time t avav ns v dd1 data retention mode t r 1.7v v dr > 1.0v figure 5. low v dd data retention waveform t efr e1 v dd2 v in <0.3v ddf2 cmos e2 v ss v in >0.7v dd2 cmos 1.7v notes: 1. 50pf including scope probe and test socket. 2. measurement of data output occurs at the low to high or high to low transition mid-point (i.e., cmos input = v dd2 /2). 90% figure 6. ac test loads and input waveforms input pulses 10% < 2ns < 2ns 1.4v 300 ohms 50pf cmos 0.0v v dd2 -0.05v
i n d e v e l o p m e n t 12 packaging 1. all exposed metalized areas are gold plated over electroplated nickel per mil-prf-38535. 2. the lid is electrically connected to v ss . 3. lead finishes are in accordance to mil-prf-38535. 4. lead position and coplanarity are not measured. 5. id mark is vendor option. figure 7. 36-pin ceramic flatpack
13 i n d e v e l o p m e n t ordering information 512k x 8 sram: ut **** * - * * * * * lead finish: (a) = hot solder dipped (c) = gold (x) = factory option (gold or solder) screening: (c) = military temperature range flow (p) = prototype flow package type: (u) = 36-lead fp access time: (10) = 10ns access time (15) = 15ns access time device type: (8r51k8) = 512k x 8 sram notes: 1. lead finish (a,c, or x) must be specified. 2. if an ?x? is specified when ordering, then the part marking will match the lead finish and will be either ?a? (solder) or ?c? (g old). 3. prototype flow per utmc manufacturing flows document. tested at 25 c only. lead finish is gold only. radiation neither tested nor guaranteed. 4. military temperature range flow per utmc manufacturing flows document. devices are tested at -55 c, room temp, and 125 c. radiation neither tested nor guaranteed.
i n d e v e l o p m e n t 14 512k x 8 sram: smd 5962 - **tbd** ** lead finish: (a) = hot solder dipped (c) = gold (x) = factory option (gold or solder) case outline: (u) = 36-lead ceramic flatpack class designator: (q) = qml class q (v) = qml class v device type (01) = 10ns access time, cmos i/o, 36-lead flatpack package, dual chip enable (02) = 15ns access time, cmos i/o, 36-lead flatpack package, dual chip enable (tbd) = 15ns access time, cmos i/o, 40-lead flatpack package, dual chip enable (not available) drawing number: tbd total dose: (r) = 100k rad(si) federal stock class designator: no options * * * notes: 1. lead finish (a,c, or x) must be specified. 2. if an ?x? is specified when ordering, part marking will match the lead finish and will be either ?a? (solder) or ?c? (gold). 3. total dose radiation must be specified when ordering. qml q and qml v not available without radiation hardening.

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